Title :
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VHDL Implementation of Programmable BIST using FSM
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Author :
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Hitanshu Saluja, Anuj
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Journal name :
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IJMRS's International Journal of Engineering Sciences, ISSN 2277-9698
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Volume :
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Volume 02, Issue 02, Jun. 2013
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Keywords :
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BIST, Low power, Address counter, Test Pattern Generators.
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Abstract :
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In today’s Integrated Circuits (IC’s) designs Built-in Self-Test (BIST) is becoming important for the memory which is the most necessary part of the System on Chip. The March algorithm has been widely used to test memory core of System on chip (SOC). LFSRs and counters are mainly used to generate the memory addresses, which can be serially applied to the memory cores under test. In this paper Address counters and Data generators (i.e. parts of the MBIST) are designed. These implemented in Hardware Description Language (HDL), and the area and power analyzed for each case.
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